(1) Field of the Invention
This invention relates to an information processor which increases the utilization of functional units, by issuing multiple instructions from different instruction streams in parallel and to an instruction scheduler used for the information processor.
(2) Description of the Related Art
Recently, higher-and-higher-speed execution of instructions in information processors is being pursued by processing them in parallel. The architectural definition of the current general-purpose computers implies sequential execution of instructions, that is, any instruction being executed after the execution of the immediately preceding instruction is completed.
Some years ago, the designers of high-performance sequential machines already knew that concurrent execution of instructions could improve the performance of the machines. First tried on this line was the pipelining (parallelization) of instruction process. However, inter-instruction dependencies (for example, the information input of an instruction is generated by executing the immediately preceding instruction) prevent these primary pipelined machines from achieving up to the upper limit performance that one instruction is executed per cycle. However, this problem has been almost solved by the advent of the Reduced Instruction Set Computer (RISC) processor, whose number of instructions to be executed per cycle is almost 1, which is close to the limit of high speed. MIPS R2000/3000 is an example of the pipelined high-performance RISC processor. However, since it is impossible to depend only on the pipelining technique to realize further improvement of the performance, the designers have provided more arithmetic units, by which multiple instructions have been issued per cycle. Such improvement of the performance costs additional amount of hardware including not only more functional units but also more complicated control in order to keep logical sequence of instruction execution demanded by the architecture. Intel 80960CA is the first commercial microprocessor employing such a superscalar (multi-instruction issue) technique.
However, there is also a limitation to improve the performance of the processors by employing such a technique. It is said that only two or three instructions could be issued in parallel because the inter-instruction dependencies are not thoroughly eliminated, taking normal application into account. (refer to "Nikkei electronics" 487 issue p.191-200)